The present application claims priority of Taiwan application serial No. 89107406, filed on Apr. 19, 2000, and the contents thereof are herein incorporated as reference.
1. Field of the Invention
The invention relates in general to a data processing system and method for accessing memory therein, and more particularly to a data processing system capable of executing and downloading programs and the method for accessing data utilizing a unified memory space therein.
2. Description of the Related Art
In the development of a data processing system, the microprocessor is a component contributing to the flexibility of the system. By appropriately changing the program executed by the microprocessor of the system, a product is capable of performing various functions for meeting various specifications required.
The microprocessors, such as the 8051-based microprocessors, are commonly found in the peripheral products of computer systems, such as image scanners, modems, and DVD-ROM drives. 8051-based microprocessors are also called microcontrollers for their self-contained functionality including the processing unit, embedded memory units, and input/output units. Inside these microprocessors, there include read only memory (ROM) and random access memory (RAM) for respectively storing the program and the data processed by the program. In addition, through the built-in input/output (I/O) ports of the microprocessor, it provides functions for system expansion. For instance, through the I/O ports, an external ROM and/or RAM can be connected to the microprocessor for expanding the physical memory space. In another instance, the built-in I/O ports can be connected to an external circuitry, such as an application specific integrated circuit (ASIC), for the purpose of controlling other components.
In the application of the microprocessor to peripherals such as scanners, modems, and DVD drives, the microprocessor acts as an agent for receiving the instructions and data through the interface of a computer system and processing and converting them into the instructions and data for the ASIC of the data processing system. According to the processed instructions and data, the ASIC controls the peripheral""s specific components, such as the optical head of a DVD drive. In addition, through the microprocessor, the status and output of the peripheral can be sent to the computer system.
In the application of the microprocessor described above, the program to be executed by the microprocessor is needed to be updated during the development of the system frequently and after leaving factory for the purpose of maintenance for resolving deficiency and adding new functionality. The most direct manner for the replacement of the contents in the ROM storing the program is to program the ROM, such as an electrical programmable ROM (EPROM), by a program writer. In practice, one approach is to design the system with the microprocessor using an external ROM to store the program. Through the replacement of the external ROM with updated version of the program or the programming of the external ROM, the purpose of updating is completed. However, the use of the external ROM increases the production cost. Further, as the kinds of products using external ROM increase, much more costs for management for the ROMs are required.
Another approach is to design the system capable of downloading a program from the external host computer to the system for execution. Utilizing the approach in the design of computer peripherals, they can download the program from a personal computer for updating the binary code of the program to be executed.
Referring now to FIG. 1, it illustrates a conventional program-downloadable data processing system 10 including a microprocessor 100, a latch 105, a boot ROM 110, a program memory 112, a data memory 114, an ASIC 150, and a memory 152 for the ASIC 150 to access. The system 10 is coupled to an external computer system 20 from which the system 10 downloads a program binary code. The microprocessor 100 is for controlling the ASIC 150. The ASIC 150 is specific-purpose multifunctional component which processes the instructions and data sent by the microprocessor 100, controls another components, and accesses the memory 152. For the storage of the downloaded program code, the microprocessor 100 is coupled to the program memory 112, such as a flash memory or static RAM (SRAM); for the system using SRAM, the program download operation must be performed every time when the system is initialized, this is what makes the difference with the flash memory. In addition, the system 10 adopts a SRAM as the data memory 114. For the downloading of the program code, the system 10 must execute a boot code for initializing the system. The boot code can be programmed into the internal ROM of the microprocessor 100 such as the boot ROM 110 shown in FIG. 1, or stored in the external ROM.
The component 100 in FIG. 1 is a microprocessor such as a standard 8051 or 8051-based microprocessor. When being coupling to an external program memory or an external data memory, the microprocessor utilizes its two I/O ports, such as PORT 0 and PORT 2 of a standard 8951 microprocessor, to form an address/data bus for communicating with the external memory. For instance in the standard 8051 microprocessor, for accessing data corresponding to a memory address, the high byte of the memory address is outputted through PORT 2 while the low byte of the memory address is outputted through PORT 0. Then, PORT 0 is used for receiving or sending the data corresponding to the memory address. In this way, a latch, such as the latch 105 in FIG. 1, must be used to cooperate to complete data access processes. In a situation that the microprocessor needs to read data from the external memory, the latch 105 stores the low byte of an address outputted through PORT 0. The output of the latch 105 and the output of PORT 2 then provide a complete 16-bit address to the address input of the external memory while PORT 0 is for reading the data from the external memory.
According to the 8951-based microprocessor""s specification, the read/write operations must involve several control signals including the address latch-enable (ALE) signal, program store enable (PSEN) signal, read strobe (RD) signal, and write strobe (WR) signal. Except the ALE signal, all of these signals are active low, i.e. the signal represents xe2x80x9cenablingxe2x80x9d when it is at a low level.
In the following, the relationship of the control signals and the clock when the 8051 microprocessor reads instructions or reads data will be described according to the timing diagrams. Referring to FIG. 2A, it illustrates the timing diagrams of the signals when the 8051 microprocessor fetches an instruction from the external program memory. In FIG. 2A, the negative edge of the ALE signal indicates that the signal provided on the bus represents a valid address signal. The negative edge triggers the latch to store the low byte of the address signal while PORT 2 outputs the high byte of the address signal. When the PSEN signal is at the low level (logic 0), it enables the external program memory 112. The bus (i.e. PORT 0) is then for receiving data. When the PSEN signal goes from the low level to the high level, the 8051 microprocessor reads the data from the program memory and regards the data as the instruction for execution.
FIG. 2A illustrates that during one machine period there are six states (S1 to S6) in which each state contains two clock cycles; thus, there are twelve clock cycles in one machine period. As can be seen in FIG. 2A, two pulses occur on the ALE signal in one machine period, corresponding to two times of fetching of instruction. If the clock cycle of the system clock is T (in sec), the width of program fetch pulse (i.e. the time of the PSEN signal in the low level) is T2, where T2=3T. Supposed that the system clock frequency is 12 MHz (the maximum clock frequency for a standard 8051 microprocessor), T=83xc3x9710xe2x88x929 sec=83 ns and T2=3T=249 ns. It implies that the external program memory, in response to an instruction fetch request, have to output the corresponding instruction within 249 ns when the microprocessor operates at 12 MHz.
Referring to FIG. 2B, it illustrates the timing diagram of signals when the 8051 microprocessor reading data from or writing data into the external data memory. For the 8051 microprocessor, the RD and WR signals are used to enable the external data memory. When the RD signal is enabled, the data memory receives the address signal and outputs the corresponding data. The microprocessor then receives the data through the bus at the positive edge of the RD signal. When the WR signal is enabled, the data of the microprocessor are outputted through the bus. The data are then written into the data memory at the positive edge of the WR signal.
When the microprocessor is to read data, the low byte of the address signal corresponding to the data is outputted through PORT 0 while the high byte of that through PORT 2. At this time, when the ALE signal goes from the high level to the low level, the negative edge triggers a latch to store the low byte of the address signal. The complete 16-bit address is then provided by the outputs of the latch and PORT 2. After that, the RD signal goes to the low level for enabling the external data memory. Referring to FIG. 2B, the time of being in the enable state of the RD signal is T4, where T4=6T. It implies that the external data memory, in response to the data read request, have to output the corresponding data within 6T.
For the details of the access of the external memory, please refer to the programming reference book and specification of the microprocessor.
As described above, in order to download the program code from the external system, external memories are necessary to be utilized as the program memory and the data memory. Besides, the timing of the control signals must meet the requirements of the specification. In this way, the production cost increases due to the use of the memory chips, such as using SRAM or flash memory, thus resulting in an increase of the total cost.
It is therefore an object of the invention to provide a data processing system, and a method for accessing memory by utilizing a unified memory space therein, where the data processing system downloads program code from an external computer system. By applying the principle of the invention, data processing systems can be implemented in a simplified structure so that the problem of an increase in cost due to the use of external memory chips is resolved. In addition, the functionality of the conventional program-downloadable data processing systems can be supported and fulfilled in the data processing system according to the invention with less components and simplified circuit layout, thus resulting in a simplified system design and reduction in total cost.
According to the object of the invention, it is achieved by providing a data processing system, including a microprocessor, an application specific integrated circuit (ASIC), and a memory. The microprocessor generates an address latch enable (ALEN) signal, a program memory enable (PMEN) signal, a read enable (RDEN) signal, a write enable (WREN) signal, and a first address signal. The ASIC is coupled between the microprocessor and the memory, wherein the ASIC operates at an operating frequency which is greater than an operating frequency that the microprocessor operates at. In the data processing system, the ASIC is utilized to communicate with an external computer system for downloading a program code from the external computer system to the memory in which the program code is stored in a memory region of the memory through the ASIC. The ASIC is for mapping the memory region onto an external memory address space of the microprocessor. The ASIC, during the enabling period of the ALEN signal, receives the first address signal outputted by the microprocessor, converts the first address signal into a second address signal corresponding to an address in the memory region, and reads a first data from the memory according to the second address signal. In response to the enable state of either the PMEN, RDEN, or WDEN signal, the ASIC processes the signals of the microprocessor as follows: (a) when the PMEN signal is enabled, the ASIC converts the first data into a second data and sends the second data to the microprocessor; (b) when the RDEN signal is enabled, the ASIC converts the first data into a second data and sends the second data to the microprocessor; and (c) when the WREN signal is enabled, the microprocessor sends a third data to the ASIC and the ASIC converts the third data into a fourth data and writes the fourth data into the memory according to the second address signal.
According to the object of the invention, it is achieved by providing a method for accessing memory in the data processing system. The data processing system includes a microprocessor, an ASIC, and a memory, and downloads a program code from an external computer system to the memory in which the program code is stored in a memory region in the memory. First, the microprocessor generates an address latch enable (ALEN) signal, a program memory enable (PMEN) signal, a read enable (RDEN) signal, a write enable (WDEN) signal, and a first address signal. The ASIC, during the enabling period of the ALEN signal, receives the first address signal, converts the first address signal into a second address signal corresponding to an address in the memory region, and reads a first data from the memory according to the second address signal. After the first data is read, in response to the enable state of either the PMEN, RDEN, or WDEN signal, the ASIC processes the associated signals of the microprocessor as follows. When the PMEN signal is enabled, the ASIC converts the first data into a second data and sends the second data to the microprocessor. When the RDEN signal is enabled, the ASIC converts the first data into a second data and sends the second data to the microprocessor. When the WREN signal is enabled, the microprocessor sends a third data to the ASIC, and then the ASIC converts the third data into a fourth data and writes the fourth data into the memory according to the second address signal.